1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device including nonvolatile memory cell transistors.
2. Description of the Related Art
EPROMs (Erasable Programmable Read Only Memory), i.e., charge-injection type nonvolatile semiconductor devices, have been manufactured by the method shown in FIGS. 5A-5D. In these figures, broken line 101 indicates the border between a memory cell and a load transistor, and broken line 102 the border between the load transistor and a peripheral circuit.
In the method, at first, a field oxide film 42 and a gate oxide film 43 are provided on a semiconductor substrate 41, as shown in FIG. 5A. The semiconductor substrate surface is coated with a resist layer 44, as shown in FIG. 5B. Using photolithography techniques, the resist film 44 is selectively removed to provide a window 46 for forming a channel region 45 of the memory cell transistor therein. Subsequently, impurity ions are implanted into the substrate through the window 46, followed by removing the resist film 44. As shown in FIG. 5C, the substrate surface is coated with a resist film 47, and using photolithography techniques, the resist film 47 is selectively removed to provide windows 50 and 51 for forming channel regions 48 and 49 of the load transistor and peripheral transistor, respectively. Thereafter, impurity ions are implanted into the substrate through these windows 50 and 51, and then the resist film 47 is removed. Finally, as shown in FIG. 5D, a floating gate 52, an oxide film 53 (provided between control and floating gates), a control gate 54, gate electrodes 55, diffused regions 56, an insulating film 57, an A1 wiring layer 58, and a passivation film 59 are successively provided.
The channel regions of the load transistors are formed by the same impurity ion implantation process (the same dose) as that of making the channel regions of enhancement type transistors used in peripheral circuits. Accordingly, each load transistor has a threshold voltage equal to that of each enhancement type transistor.
The semiconductor memory device described above, however, has the following disadvantage.
In general, the peripheral circuit includes at least one enhancement type transistor whose source potential is different from the substrate potential. The substrate is then biased relative to the source of the enhancement type transistor. Therefore, the threshold voltage may be increased under an operating condition in the enhancement type transistor of the peripheral circuit. The threshold voltage is usually measured in a state in which the source and the substrate of the transistor are kept at the same potential. The threshold voltage may be also increased in each enhancement type load transistor connected to each memory cell transistor, because the source of the load transistor is not kept at the same potential as that of the substrate. In the enhancement type load transistor connected to the memory cell transistor, a voltage drop corresponding to the threshold voltage (Vth) may occur, which will make the voltage applied to the memory cell transistor lower than the voltage applied to a power supply voltage terminal. When the voltage applied to the memory cell transistor is lowered, the electric field between the drain and source regions may be decreased to reduce the quantity of generated carrier. Consequently, the writing speed to the memory cell may be lowered.
On the one hand, since current leakage occurs between the source and drain regions of the transistors in the peripheral circuits, it is not possible to set the threshold voltage of each enhancement type transistor at a low value. On the other hand, each enhancement type load transistor has a comparatively long gate length (L poly), so the problem of the current leadkage may not occur. Therefore, it may be possible to set the threshold voltage at a low value.
As described above, in the conventional semiconductor memory device including charge-injection type nonvolatile memory cell transistors, the voltage applied from the power supply may be greatly lowered in the enhancement type load transistors, thereby decreasing the writing speed into the memory cells.